]> git.baikalelectronics.ru Git - kernel.git/commit
KVM: x86: Prevent KVM SVM from loading on kernels with 5-level paging
authorSean Christopherson <seanjc@google.com>
Wed, 5 May 2021 20:42:21 +0000 (13:42 -0700)
committerPaolo Bonzini <pbonzini@redhat.com>
Fri, 7 May 2021 10:06:21 +0000 (06:06 -0400)
commite043ed761201973e0fcca0b121ddd6f892df7bf2
tree1b274a3de67897c62551e988622a4cd327e37a4c
parent9714f75ce0260e6fd7b1ae7ed1c6721526903647
KVM: x86: Prevent KVM SVM from loading on kernels with 5-level paging

Disallow loading KVM SVM if 5-level paging is supported.  In theory, NPT
for L1 should simply work, but there unknowns with respect to how the
guest's MAXPHYADDR will be handled by hardware.

Nested NPT is more problematic, as running an L1 VMM that is using
2-level page tables requires stacking single-entry PDP and PML4 tables in
KVM's NPT for L2, as there are no equivalent entries in L1's NPT to
shadow.  Barring hardware magic, for 5-level paging, KVM would need stack
another layer to handle PML5.

Opportunistically rename the lm_root pointer, which is used for the
aforementioned stacking when shadowing 2-level L1 NPT, to pml4_root to
call out that it's specifically for PML4.

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210505204221.1934471-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/include/asm/kvm_host.h
arch/x86/kvm/mmu/mmu.c
arch/x86/kvm/svm/svm.c