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arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list
authorWei Li <liwei391@huawei.com>
Fri, 20 Dec 2019 09:17:10 +0000 (17:17 +0800)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 20 Dec 2019 17:57:22 +0000 (17:57 +0000)
commitdc5c0ba1201bb25834d9e70137a6c4c68348235b
treea90189c82066ee002830839ccb461a6d626f3893tree | snapshot
parent1e40f789cd97437569b2c2bf5bbd74e012223530commit | diff
arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list

HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
whitelist the MIDR in the safe list.

Signed-off-by: Wei Li <liwei391@huawei.com>
[hanjun: re-write the commit log]
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/kernel/cpu_errata.c diff | blob | history
Linux Kernel Source Tree.