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(parent: fe147a7) | patch
clk: meson: axg: fix the od shift of the sys_pll
authorYixun Lan <yixun.lan@amlogic.com>
Fri, 19 Jan 2018 02:09:26 +0000 (10:09 +0800)
committerJerome Brunet <jbrunet@baylibre.com>
Mon, 12 Feb 2018 08:49:23 +0000 (09:49 +0100)
commitdc356a2c9dc9a00c95588eb3cc64d254fd996795
tree9cd80ca23d8e175876fb35fedbba445bbb8d8368tree | snapshot
parentfe147a7b2fe12651d9c3bf0ec9b0336def474a53commit | diff
clk: meson: axg: fix the od shift of the sys_pll

According to the datasheet, the od shift of sys_pll is actually 16.

Fixes: de6d8b0529f9 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/axg.c diff | blob | history
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