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Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms
authorVarun Wadekar <vwadekar@nvidia.com>
Fri, 23 Mar 2018 17:44:40 +0000 (10:44 -0700)
committerVarun Wadekar <vwadekar@nvidia.com>
Thu, 23 Jan 2020 17:02:29 +0000 (09:02 -0800)
commitdb891f32f6c2100beb6c7d8eedcab2df57df632f
tree59db68cb28a53c34e6678dd9f1b6281fddbc8955tree | snapshot
parentceb12020fb05001777b0868b5e064dd26fd4895acommit | diff
Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms

Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.

This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.

Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c diff | blob | history
plat/nvidia/tegra/soc/t194/plat_setup.c diff | blob | history
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