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(parent: cca220e) | patch
spi: fsl-dspi: Add ~50ns delay between cs and sck
authorAaron Brice <aaron.brice@datasoft.com>
Fri, 3 Apr 2015 20:39:31 +0000 (13:39 -0700)
committerMark Brown <broonie@kernel.org>
Mon, 6 Apr 2015 17:12:25 +0000 (18:12 +0100)
commitda10b02e7799d5a1a2e27b1fe8c1b76546e37d1a
tree61b3f2885d7c8f8d3a7cbe2c36fd1bd7b001498atree | snapshot
parentcca220eddcd99606ab70f7af819ddae0787e23d8commit | diff
spi: fsl-dspi: Add ~50ns delay between cs and sck

Add delay between chip select and clock signals, before clock starts and
after clock stops.

Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-fsl-dspi.c diff | blob | history
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