git.baikalelectronics.ru Git - kernel.git/commit

]> git.baikalelectronics.ru Git - kernel.git/commit

author	Tom St Denis <tom.stdenis@amd.com>
	Thu, 11 Jun 2020 11:54:13 +0000 (07:54 -0400)
committer	Alex Deucher <alexander.deucher@amd.com>
	Wed, 1 Jul 2020 05:59:19 +0000 (01:59 -0400)
commit	d21da60fd2dbb265be1f7a900bc9b75c91906156
tree	18230fd18156acb229eee5b2efe95b5633b83163	tree \| snapshot
parent	101d271b62aeb51b1fb48fa57e10968bd200fb6c	commit \| diff

drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits

Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Linux Kernel Source Tree.

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h		diff \| blob \| history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h		diff \| blob \| history