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cxl: Configure the PSL for two CAPI ports on POWER8NVL
authorPhilippe Bergheaud <felix@linux.vnet.ibm.com>
Thu, 31 Mar 2016 09:19:28 +0000 (11:19 +0200)
committerMichael Ellerman <mpe@ellerman.id.au>
Mon, 11 Apr 2016 10:30:46 +0000 (20:30 +1000)
commitcf222330c254a271252c549d2c20b1c225af610f
treee72b91e5712e1c8b6ef742d94ba0dbf976ddd585tree | snapshot
parente48e20957c4b23953754137976455b647b40dd3fcommit | diff
cxl: Configure the PSL for two CAPI ports on POWER8NVL

The POWER8NVL chip has two CAPI ports.  Configure the PSL to route
data to the port corresponding to the CAPP unit.

Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
drivers/misc/cxl/pci.c diff | blob | history
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