soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD

soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD

[ Upstream commit b814eda949c324791580003303aa608761cfde3f ]

NXP internal information shows that the PHY refclk is gated by the
GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
LCDIF being already active, tie this bit to the HDMI_TX_PHY power
domain.

Fixes: be2b68f88318 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>