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(parent: e1ecf04) | patch
rockchip: clock: rk3036: some fix according TRM
authorKever Yang <kever.yang@rock-chips.com>
Mon, 15 May 2017 12:52:16 +0000 (20:52 +0800)
committerSimon Glass <sjg@chromium.org>
Wed, 7 Jun 2017 13:29:20 +0000 (07:29 -0600)
commitc7bde51dbf33eaff963c8f481c64407b4e7b72c8
tree30f953ef8d11259b60f5603cdd4bd4ad4d2a9b71tree | snapshot
parente1ecf04e020a3c1b84753c7b9734c80b4ff61415commit | diff
rockchip: clock: rk3036: some fix according TRM

- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch/arm/include/asm/arch-rockchip/cru_rk3036.h diff | blob | history
drivers/clk/rockchip/clk_rk3036.c diff | blob | history
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