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(parent: d3a6b34) | patch
drm/radeon: fix vm page table block size calculation
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 15 Oct 2014 21:20:55 +0000 (17:20 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 16 Oct 2014 22:34:09 +0000 (18:34 -0400)
commitc6e17235cea4e0cc83efadd4844583c8b7dde2d7
tree72d79bcfa0252136570760964444792ecfb17a5etree | snapshot
parentd3a6b34701d79ec24f1d7c70b93287309db45f03commit | diff
drm/radeon: fix vm page table block size calculation

The page offset is 12 bits.  For example if we have an
8 GB VM, we'd need 33 bits.  The number of bits needed
for PD + PT is 21 (33 - 12 or log2(8) + 18), not 20
(log2(8) + 17).

Noticed by Alexey during code review.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/radeon/radeon_device.c diff | blob | history
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