perf vendor events: For the Arm Neoverse N2

perf vendor events: For the Arm Neoverse N2

Updates the common and microarch json file to add counters available in
the Arm Neoverse N2 chip, but should also apply to other ArmV8 and ArmV9
cpus.  Specified in ArmV8 architecture reference manual

  https://developer.arm.com/documentation/ddi0487/gb/?lang=en

Some of the counters added to armv8-common-and-microarch.json are
specified in the ArmV9 architecture reference manual supplement
(issue A.a):

  https://developer.arm.com/documentation/ddi0608/aa

The additional ArmV9 counters are

  TRB_WRAP
  TRCEXTOUT0
  TRCEXTOUT1
  TRCEXTOUT2
  TRCEXTOUT3
  CTI_TRIGOUT4
  CTI_TRIGOUT5
  CTI_TRIGOUT6
  CTI_TRIGOUT7

This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
perf list to output the counter names in categories.

Counters on the Neoverse N2 are stated in its reference manual:

  https://developer.arm.com/documentation/102099/0000

Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20211210123706.7490-2-andrew.kilroy@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>