]> git.baikalelectronics.ru Git - kernel.git/commit
cxl/mem: Validate port connectivity before dvsec ranges
authorDan Williams <dan.j.williams@intel.com>
Wed, 18 May 2022 23:34:37 +0000 (16:34 -0700)
committerDan Williams <dan.j.williams@intel.com>
Thu, 19 May 2022 15:50:41 +0000 (08:50 -0700)
commitc49ff9dd8db771fd57a7b2a2054aa78f96409f8a
treed373d2e53dea658a33c505278244c38bfea115a0
parentec25379a2477b0ab76401f62d4c175c4df5ff318
cxl/mem: Validate port connectivity before dvsec ranges

In preparation for validating DVSEC ranges against the platform declared
CXL memory ranges (ACPI CFMWS) move port enumeration before the
endpoint's decoder validation. Ultimately this logic will move to the
port driver, but create a bisect point before that larger move.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291687749.1426646.18091538443879226995.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/mem.c