]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915/gvt: Align render mmio list to cacheline
authorChangbin Du <changbin.du@intel.com>
Thu, 6 Apr 2017 02:55:02 +0000 (10:55 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Wed, 12 Apr 2017 05:57:42 +0000 (13:57 +0800)
commitc3e03c7d9232c6c0cbb423daee726ca6bffcbeb5
tree16faf6807220b91820833a47fcc9818a93a46801
parentcfe4313150126d72fa1c38d61f19f416ecb9593c
drm/i915/gvt: Align render mmio list to cacheline

Make the global mmio list be cacheline aligned to improve performance.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/render.c