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(parent: 6a96f33) | patch
drm/i915: Only apply the SNB pipe control w/a to gen6
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 20 Jul 2012 17:02:28 +0000 (18:02 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 8 Aug 2012 07:34:32 +0000 (09:34 +0200)
commitc305c2db946bef347ab527f5112e52f750e083ad
tree188e1c0c4381913f1a2e16f2509704672e7689ddtree | snapshot
parent6a96f33a269fd7e6513313b434b6a76ce98d8982commit | diff
drm/i915: Only apply the SNB pipe control w/a to gen6

The requirements for the sync flush to be emitted prior to the render
cache flush is only true for SandyBridge. On IvyBridge and friends we
can just emit the flushes with an inline CS stall.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | history
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