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drm/i915/icl: Define data/clock lanes dphy timing registers
authorMadhav Chauhan <madhav.chauhan@intel.com>
Sun, 16 Sep 2018 10:53:28 +0000 (16:23 +0530)
committerJani Nikula <jani.nikula@intel.com>
Wed, 26 Sep 2018 12:52:26 +0000 (15:52 +0300)
commitc0bc09f593645a62507d39b1a5dde7345af9f2af
treec7fdd6798fdd4ea25272ac4672b4dc071159a68ctree | snapshot
parente4e7865c115bf3b5fd905cb9657f9ac0850f55f0commit | diff
drm/i915/icl: Define data/clock lanes dphy timing registers

This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.

v2: Define mask/shift for bitfields and keep names as per BSPEC (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-6-git-send-email-madhav.chauhan@intel.com
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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