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(parent: 6d25199) | patch
i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz
authorYe Li <ye.li@nxp.com>
Mon, 22 Jul 2019 01:25:03 +0000 (01:25 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 8 Oct 2019 14:35:16 +0000 (16:35 +0200)
commitc08096d296ca8f0b49ef9bb9efd14713e19b4bcb
treec66f5df45fa1f1cd87ce256a4ae160cb1486b145tree | snapshot
parent6d251996cd75f0c92d4f06e9e07fc31df7702c52commit | diff
i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz

The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider
set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU
is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28)
to workaround the problem. The correct fix should let GPU handle the
clock rate in kernel.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/mach-imx/mx7ulp/clock.c diff | blob | history
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