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(parent: 617537d) | patch
ARM: vexpress/dcscb: fix cache disabling sequences
authorNicolas Pitre <nicolas.pitre@linaro.org>
Wed, 17 Jul 2013 00:59:53 +0000 (20:59 -0400)
committerNicolas Pitre <nicolas.pitre@linaro.org>
Mon, 22 Jul 2013 16:26:09 +0000 (12:26 -0400)
commitc032671e3c45029fed35e9782a93ec30f3a52f9c
tree730257640b01d6b83b3a37d0c4961e0189faaddctree | snapshot
parent617537d2ebf9f8060e43c17ed9a7bf6d98b03f36commit | diff
ARM: vexpress/dcscb: fix cache disabling sequences

Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared.  Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
arch/arm/mach-vexpress/dcscb.c diff | blob | history
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