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ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
authorNishanth Menon <nm@ti.com>
Tue, 24 May 2016 13:35:38 +0000 (08:35 -0500)
committerTony Lindgren <tony@atomide.com>
Mon, 13 Jun 2016 08:04:01 +0000 (01:04 -0700)
commitbf16f4cba1f70cca964bf9c285d2c44f2b53d481
tree4de35453bbf0675757a62560ddffdd432810aff1tree | snapshot
parent16358b73acd523d4c17e9fe457e160eac6857db5commit | diff
ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON

As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), L4Per and L3init power domains now operate in
always "ON" mode due to asymmetric aging limitations. Update the same

[1] http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/powerdomains7xx_data.c diff | blob | history
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