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(parent: d1157ce) | patch
powerpc/perf: Add missing L2 constraint handling in Power7 PMU
authorMichael Ellerman <michael@ellerman.id.au>
Tue, 30 Oct 2012 16:09:56 +0000 (16:09 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Thu, 15 Nov 2012 02:00:36 +0000 (13:00 +1100)
commitbdef71d89cddee18b726327157a1aa772b0b5b94
tree4854509b69457adb40f1a82fb853920208c99238tree | snapshot
parentd1157ce7cf99d1eed845f7a91a8bc914919ae982commit | diff
powerpc/perf: Add missing L2 constraint handling in Power7 PMU

If we have two cache events that require different settings of the L2SEL
bits in MMCR1 then we can not schedule those events simultaneously. Add
logic to the constraint handling to express that.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/perf/power7-pmu.c diff | blob | history
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