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clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
authorBiju Das <biju.das.jz@bp.renesas.com>
Fri, 3 Dec 2021 11:51:49 +0000 (11:51 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 8 Dec 2021 09:05:56 +0000 (10:05 +0100)
commitbb6309f27fb1e20a1c69600a8542ad07fa773270
tree64135980167e655a9ff3932c2ed1ffbaedcd64bbtree | snapshot
parentad4efb50f6f2fcf5c8f01e64de80359893c2e7b2commit | diff
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro

Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree
mentioned in the hardware manual(Rev.1.00 Sep, 2021).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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