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(parent: b7bd986) | patch
feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC
authorSieu Mun Tang <sieu.mun.tang@intel.com>
Thu, 5 May 2022 15:42:55 +0000 (23:42 +0800)
committerSieu Mun Tang <sieu.mun.tang@intel.com>
Thu, 5 May 2022 15:47:20 +0000 (23:47 +0800)
commitbb0fcc7e011ec4319a79734ba44353015860e39f
tree98ed67adba942403174930384999e90356a864ectree | snapshot
parentb7bd9863dc2f0a055e0c4bc065e071c4b1863647commit | diff
feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC

SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc
plat/intel/soc/stratix10/bl2_plat_setup.c diff | blob | history
plat/intel/soc/stratix10/include/s10_clock_manager.h diff | blob | history
plat/intel/soc/stratix10/include/s10_mmc.h [new file with mode: 0644] blob
plat/intel/soc/stratix10/platform.mk diff | blob | history
plat/intel/soc/stratix10/soc/s10_mmc.c [new file with mode: 0644] blob
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