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(parent: 31b20cd) | patch
net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail
authorBiao Huang <biao.huang@mediatek.com>
Fri, 24 May 2019 06:26:09 +0000 (14:26 +0800)
committerDavid S. Miller <davem@davemloft.net>
Sat, 25 May 2019 18:02:31 +0000 (11:02 -0700)
commitbafc3941e97d42a35558c1c60f5b4fc55c653e4e
tree5c28de197a879032f2fa9be19eb49c6eddad048ctree | snapshot
parent31b20cdef882c63697e16dc8b6f86141320f5a1ecommit | diff
net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail

1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.

Fixes: 017761c180cf ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c diff | blob | history
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