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(parent: 7ba961a) | patch
ARM: invalidate L1 before enabling coherency
authorRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 8 Jul 2015 23:30:24 +0000 (00:30 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 17 Jul 2015 14:08:40 +0000 (15:08 +0100)
commitb54f013f684a0d05f5348bd22dc93906df6ae14c
tree5e7b392f695b499cbb257caba47caac36a0fb963tree | snapshot
parent7ba961abba882853bf926038d7aa5d1694d7910fcommit | diff
ARM: invalidate L1 before enabling coherency

We must invalidate the L1 cache before enabling coherency, otherwise
secondary CPUs can inject invalid cache lines into the coherent CPU
cluster, which could then be migrated to other CPUs.  This fixes a
recent regression with SoCFPGA randomly failing to boot.

Fixes: 5a91c156346f ("ARM: v7 setup function should invalidate L1 cache")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/proc-v7.S diff | blob | history
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