]> git.baikalelectronics.ru Git - kernel.git/commit
riscv,entry: fix misaligned base for excp_vect_table
authorZihao Yu <yuzihao@ict.ac.cn>
Wed, 17 Mar 2021 08:17:25 +0000 (16:17 +0800)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Fri, 2 Apr 2021 04:37:05 +0000 (21:37 -0700)
commitb4587b957a3bd9e06400becf855ad86458de75ec
treec30bba6025078108ef26dadf653ac8083b0941af
parentcaa52099a99ee01ea8f1bfab533c7c5c980e2eec
riscv,entry: fix misaligned base for excp_vect_table

In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
arch/riscv/kernel/entry.S