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(parent: 24b7c9a) | patch
clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
authorJonas Karlman <jonas@kwiboo.se>
Fri, 4 Aug 2023 09:33:59 +0000 (09:33 +0000)
committerKever Yang <kever.yang@rock-chips.com>
Sat, 12 Aug 2023 02:35:35 +0000 (10:35 +0800)
commitaf022a912c71d5356a1a7550919b89665a9936ed
tree9d3c048a08ce7d74434eedc808996281387cc564tree | snapshot
parent24b7c9af0c7745b259099268bade81597e289f65commit | diff
clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div

The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.

Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.

Fixes: 8efd0358e439 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/include/asm/arch-rockchip/cru_rk3568.h diff | blob | history
drivers/clk/rockchip/clk_rk3568.c diff | blob | history
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