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(parent: d2dd5f7) | patch
arm: zynq: Remove fclk-enable property for cse-nor target
authorMichal Simek <michal.simek@xilinx.com>
Fri, 20 Jul 2018 08:16:21 +0000 (10:16 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 6 Aug 2018 06:44:35 +0000 (08:44 +0200)
commitaef842290b36eb73d268e538c29954041184f6d8
tree0be9bfe26a63ffa1f952071407c587b7a1838e39tree | snapshot
parentd2dd5f7bd76d148c3eb0396d4b641f25e30c34c6commit | diff
arm: zynq: Remove fclk-enable property for cse-nor target

Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/zynq-cse-nor.dts diff | blob | history
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