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| author | Tien Hock Loh <tien.hock.loh@intel.com> | |
| Mon, 11 May 2020 08:11:39 +0000 (01:11 -0700) | ||
| committer | Manish Pandey <manish.pandey2@arm.com> | |
| Mon, 8 Jun 2020 22:03:34 +0000 (22:03 +0000) | ||
| commit | aea772dd7aa85681a9ead19cad4ead1732bbc003 | |
| tree | 45f096232af0d8df97b6bb2809234005b09bb559 | tree | snapshot |
| parent | fa09d54454e91ee9fcb157a8134e18dd070ed957 | commit | diff |
| plat/intel/soc/agilex/bl2_plat_setup.c | diff | blob | history | |
| plat/intel/soc/agilex/include/agilex_clock_manager.h | diff | blob | history | |
| plat/intel/soc/agilex/include/agilex_mmc.h | [new file with mode: 0644] | blob |
| plat/intel/soc/agilex/platform.mk | diff | blob | history | |
| plat/intel/soc/agilex/soc/agilex_mmc.c | [new file with mode: 0644] | blob |
| plat/intel/soc/common/include/socfpga_system_manager.h | diff | blob | history |