]> git.baikalelectronics.ru Git - arm-tf.git/commit
plat: intel: set DRVSEL and SMPLSEL for DWMMC
authorTien Hock Loh <tien.hock.loh@intel.com>
Mon, 11 May 2020 08:11:39 +0000 (01:11 -0700)
committerManish Pandey <manish.pandey2@arm.com>
Mon, 8 Jun 2020 22:03:34 +0000 (22:03 +0000)
commitaea772dd7aa85681a9ead19cad4ead1732bbc003
tree45f096232af0d8df97b6bb2809234005b09bb559
parentfa09d54454e91ee9fcb157a8134e18dd070ed957
plat: intel: set DRVSEL and SMPLSEL for DWMMC

DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
plat/intel/soc/agilex/bl2_plat_setup.c
plat/intel/soc/agilex/include/agilex_clock_manager.h
plat/intel/soc/agilex/include/agilex_mmc.h [new file with mode: 0644]
plat/intel/soc/agilex/platform.mk
plat/intel/soc/agilex/soc/agilex_mmc.c [new file with mode: 0644]
plat/intel/soc/common/include/socfpga_system_manager.h