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(parent: 21777f7) | patch
clk: stm32f4: fix timeout management for pll and ready gate
authorGabriel Fernandez <gabriel.fernandez@st.com>
Thu, 16 Mar 2017 08:16:41 +0000 (09:16 +0100)
committerMichael Turquette <mturquette@baylibre.com>
Wed, 12 Apr 2017 16:50:56 +0000 (18:50 +0200)
commitad3a3594b78dc0d86fbda8908bf773b5eda8861a
treeedabb6be5fc1fa580b0a7d7c61f141f93d263980tree | snapshot
parent21777f7c235c1fb66b729257db7d5e13b8905ab6commit | diff
clk: stm32f4: fix timeout management for pll and ready gate

Use a classic polling to test bit ready.
And the shift of the bit ready of LSE & LSI were wrongs.

Fixes: 0488c1fb522c ("clk: stm32f4: Add LSI & LSE clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drivers/clk/clk-stm32f4.c diff | blob | history
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