]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: set CDCLK if DPLL0 enabled during resuming from S3
authorGary Wang <gary.c.wang@intel.com>
Fri, 28 Aug 2015 08:40:34 +0000 (16:40 +0800)
committerJani Nikula <jani.nikula@intel.com>
Fri, 28 Aug 2015 17:32:02 +0000 (20:32 +0300)
commita482f70edc5b42b30823c8a132c22833e63be90d
treeeea09ddab62b4a401defa651afa1a4fd3f74e42e
parent926c346ed7ba218523c37b831a28649a2e8c4fa6
drm/i915: set CDCLK if DPLL0 enabled during resuming from S3

Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then
driver needs to set CDCLK to avoid display corruption if DPLL0 enabled.

References: https://bugs.freedesktop.org/show_bug.cgi?id=91697
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Cooper Chiou <cooper.chiou@intel.com>
Reviewed-by: Wei Shun Chang <wei.shun.chang@intel.com>
Tested-by: Gary Wang <gary.c.wang@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Gavin Hindman <gavin.hindman@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Xiong Y Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Gary Wang <gary.c.wang@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_display.c