]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915/icl: Implement gen11 flush including tile cache
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Thu, 15 Aug 2019 08:30:53 +0000 (11:30 +0300)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 15 Aug 2019 12:13:23 +0000 (13:13 +0100)
commit9fd3a2fc1389d6c2a81656c89a44223fceb5c365
tree8d880e2b7b8fff38a377ed182c0e62c08ef22539
parent7ce012b54c1d8ae6057f4f903908d17bc071fb02
drm/i915/icl: Implement gen11 flush including tile cache

Add tile cache flushing for gen11. To relive us from the
burden of previous obsolete workarounds, make a dedicated
flush/invalidate callback for gen11.

To fortify an independent single flush, do post
sync op as there are indications that without it
we don't flush everything. This should also make this
callback more readily usable in tgl (see l3 fabric flush).

v2: whitespacing

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190815083055.14132-1-mika.kuoppala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_gpu_commands.h
drivers/gpu/drm/i915/gt/intel_lrc.c