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riscv: cpu: check U-Mode before counteren write
authorNikita Shubin <n.shubin@yadro.com>
Wed, 14 Dec 2022 05:58:43 +0000 (08:58 +0300)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 1 Feb 2023 08:17:13 +0000 (16:17 +0800)
commit9faf432b8145df4685d58477bc26b4af92261168
tree71fa3178e46d5e00e95163f4409cbdca4ee093b8tree | snapshot
parent27bef468dcd9f5869118882f939494a5331ecd7acommit | diff
riscv: cpu: check U-Mode before counteren write

The Priv ISA states:
"In systems without U-mode, the mcounteren register should
not exist."

Check U-Mode is present in MISA before writing to counteren, otherwise
we endup with Illegal Instruction exception on systems without U-Mode.

Also make checking MISA default for M-Mode.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/cpu.c diff | blob | history
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