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(parent: 5a6848e) | patch
riscv: jh7110: enable riscv,timer in the device tree
authorTorsten Duwe <duwe@lst.de>
Mon, 14 Aug 2023 16:05:33 +0000 (18:05 +0200)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 5 Sep 2023 02:53:36 +0000 (10:53 +0800)
commit9eb732d9850622c6510923fc2e6b5af7bf5bdb30
tree6f46d4b8d5e9cad5f969665f707d0b7374ef9130tree | snapshot
parent5a6848e06552495c60e27d542a8e3f271ebc185bcommit | diff
riscv: jh7110: enable riscv,timer in the device tree

The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/dts/jh7110.dtsi diff | blob | history
"Das U-Boot" Source Tree.