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(parent: 6358001) | patch
drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0
authorTim Huang <tim.huang@amd.com>
Mon, 15 Aug 2022 05:03:49 +0000 (13:03 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 25 Aug 2022 17:52:48 +0000 (13:52 -0400)
commit9e6f2cd4fc16e97edf109e6f158472d977d03d5a
treef15785748212ade8f9801033fb758e30085a18cctree | snapshot
parent63580012fbab54e65d1fcadccbc56f36039eec31commit | diff
drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0

Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h diff | blob | history
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