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(parent: d8dce73) | patch
clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
authorAndrew Jeffery <andrew@aj.id.au>
Thu, 10 Oct 2019 02:06:55 +0000 (12:36 +1030)
committerStephen Boyd <sboyd@kernel.org>
Tue, 26 Nov 2019 18:02:48 +0000 (10:02 -0800)
commit9da84a0a977c1f6bb68d383da450ef7b7a72be78
tree4fe5be9b06248ae006cd17eebfde32c9cd5ec0a8tree | snapshot
parentd8dce737696134b9ef53bc0f15f441101a80201dcommit | diff
clk: aspeed: Add RMII RCLK gates for both AST2500 MACs

RCLK is a fixed 50MHz clock derived from HPLL that is described by a
single gate for each MAC.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20191010020655.3776-3-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-aspeed.c diff | blob | history
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