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MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
authorThomas Bogendoerfer <tsbogend@alpha.franken.de>
Mon, 14 Sep 2020 16:05:00 +0000 (18:05 +0200)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Tue, 15 Sep 2020 08:40:29 +0000 (10:40 +0200)
commit9cecb594bc4c51acb23474a2acdfe82cf0aaca18
tree1c8500388f9aada05ebd9958f2b26b30c72b132ftree | snapshot
parentaf5a6404a7f78fa4d8f21bd12c7053bdbe2d9b02commit | diff
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

Commit c6e1cdd64357 ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: c6e1cdd64357 ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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