]> git.baikalelectronics.ru Git - uboot.git/commit
projects / uboot.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c48ab18) | patch
riscv: Add exception codes for xcause register
authorBin Meng <bmeng.cn@gmail.com>
Wed, 12 Dec 2018 14:12:37 +0000 (06:12 -0800)
committerAndes <uboot@andestech.com>
Tue, 18 Dec 2018 01:56:27 +0000 (09:56 +0800)
commit9ad2233b8813fd8ae8e732c7441d2e1dfed06425
tree4a1a5d03f2c44920b250cf9f3b1ad826f3634d8dtree | snapshot
parentc48ab183e1122d2518a9120bece9aef8f2e110c2commit | diff
riscv: Add exception codes for xcause register

This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/encoding.h diff | blob | history
"Das U-Boot" Source Tree.