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microblaze: Define correct L1_CACHE_SHIFT value
authorMichal Simek <monstr@monstr.eu>
Mon, 26 Apr 2010 11:43:23 +0000 (13:43 +0200)
committerMichal Simek <monstr@monstr.eu>
Thu, 6 May 2010 09:21:59 +0000 (11:21 +0200)
commit98563557b26579d8eb3e0f52789dc73d7e72dbf6
tree19f8a929ce264068a21b25b91258afe4bad64b75tree | snapshot
parenta46fd8189a96602aebed34addec639a155505e06commit | diff
microblaze: Define correct L1_CACHE_SHIFT value

Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8  32bit=4Byte values
which is corresponding with SHIFT 5.

Signed-off-by: Michal Simek <monstr@monstr.eu>
arch/microblaze/include/asm/cache.h diff | blob | history
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