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(parent: 7b5f17c) | patch
drm/amdgpu: Add CLK IP base offset
authorRex Zhu <rex.zhu@amd.com>
Thu, 5 Jul 2018 08:34:13 +0000 (16:34 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 10 Jul 2018 19:16:39 +0000 (14:16 -0500)
commit980f3a1f79353380a24618ffcf17d6459ee083e1
treef17d07fe289e897ad5245eb6a80252841cb3803ctree | snapshot
parent7b5f17cef1199737d78b2a35ec3633b0149691c1commit | diff
drm/amdgpu: Add CLK IP base offset

so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h diff | blob | history
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c diff | blob | history
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