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(parent: 2ae118c) | patch
drm/amdgpu: Set CP_HQD_PQ_CONTROL.RPTR_BLOCK_SIZE correctly
authorHaohui Mai <ricetons@gmail.com>
Tue, 17 May 2022 06:06:35 +0000 (23:06 -0700)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 26 May 2022 18:56:31 +0000 (14:56 -0400)
commit973b6c007c8d907a4c2b76f9d19329fa2b76bac0
treea69042584719def282b1234a98c5b5ee25fa164etree | snapshot
parent2ae118c8e5e7636efbf21c692a99d1beb254b010commit | diff
drm/amdgpu: Set CP_HQD_PQ_CONTROL.RPTR_BLOCK_SIZE correctly

Remove the accidental shifts on the values of RPTR_BLOCK_SIZE
in gfx_v8-v11. The bug essentially always programs the
corresponding fields to zero instead of the correct value.
The hardware clamps the min value to 5 so this resulted in a
value of 5 being programmed.

Signed-off-by: Haohui Mai <ricetons@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c diff | blob | history
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