]> git.baikalelectronics.ru Git - kernel.git/commit
net/mlx5e: Use CQE padding for Ethernet CQs
authorDaniel Jurgens <danielj@mellanox.com>
Mon, 5 Nov 2018 22:05:37 +0000 (16:05 -0600)
committerSaeed Mahameed <saeedm@mellanox.com>
Tue, 11 Dec 2018 22:52:20 +0000 (14:52 -0800)
commit96cff998db01368927f6bc0102788040b495211c
treedc42835752a817f639508f23b45b1601fd644861
parent4930bd00531ce281ca7b7c7f766c574bfaea33e2
net/mlx5e: Use CQE padding for Ethernet CQs

Writing 64B CQEs to 128B cache lines results in a RMW operation. Padding
the CQEs to 128B if possible improves performance on 128B cache line
systems like PPC.

Testing on PPC showed up to a 24% improvement in small packet throughput
vs the default behavior, depending on the workload and system topology.

Signed-off-by: Daniel Jurgens <danielj@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/ethernet/mellanox/mlx5/core/wq.c
drivers/net/ethernet/mellanox/mlx5/core/wq.h
include/linux/mlx5/cq.h