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(parent: c893e6c) | patch
drm/msm/a6xx: Send the right perf index value to GMU
authorSharat Masetty <smasetty@codeaurora.org>
Thu, 27 Sep 2018 16:46:22 +0000 (22:16 +0530)
committerRob Clark <robdclark@gmail.com>
Thu, 4 Oct 2018 00:24:54 +0000 (20:24 -0400)
commit96cb86f495b3959675d583890b0bea41910b3195
tree0f9aa5738480512e3593cfd321869bf70e8bc133tree | snapshot
parentc893e6cb11bf6e88585b9da2f4ff88475c1a41e0commit | diff
drm/msm/a6xx: Send the right perf index value to GMU

The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/adreno/a6xx_gmu.c diff | blob | history
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