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(parent: d3a5e9f) | patch
drm/nouveau/ltc/gp10b: Add custom L2 cache implementation
authorThierry Reding <treding@nvidia.com>
Mon, 9 Dec 2019 12:00:04 +0000 (13:00 +0100)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 15 Jan 2020 00:49:59 +0000 (10:49 +1000)
commit95478b29b192934d54dbe25db25a1607baf4c11c
tree6c7b57f1c2c9e2424fe05157686d58c5917fb573tree | snapshot
parentd3a5e9f7c55d325c4798988faff7ac94b781be2dcommit | diff
drm/nouveau/ltc/gp10b: Add custom L2 cache implementation

There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h diff | blob | history
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c diff | blob | history
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild diff | blob | history
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c [new file with mode: 0644] blob
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h diff | blob | history
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