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(parent: 68eebf6) | patch
ARM: socfpga: Disable D cache in SPL
authorMarek Vasut <marex@denx.de>
Tue, 8 May 2018 18:32:01 +0000 (20:32 +0200)
committerMarek Vasut <marex@denx.de>
Sat, 9 Mar 2019 16:59:13 +0000 (17:59 +0100)
commit94f8d19e3644918f2025e64a15e9fdbbe8573f27
tree154edeedce6b844c79ee7aaa325f5f51d6e03b0etree | snapshot
parent68eebf62be92499213020369a4976d9453091288commit | diff
ARM: socfpga: Disable D cache in SPL

The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
arch/arm/mach-socfpga/spl_a10.c diff | blob | history
include/configs/socfpga_arria10_socdk.h diff | blob | history
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