]> git.baikalelectronics.ru Git - kernel.git/commit
octeontx2-pf: Use hardware register for CQE count
authorGeetha sowjanya <gakula@marvell.com>
Tue, 28 Sep 2021 05:55:26 +0000 (11:25 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 28 Sep 2021 13:10:24 +0000 (14:10 +0100)
commit92d39c755ba8e4e6e504fb1f8993c842e4363ecc
tree836de45caa99a753010ba58e732f6d1969f731e5
parent8950c2870b80b77d7f1f0e984b903ba2121c9b42
octeontx2-pf: Use hardware register for CQE count

Current driver uses software CQ head pointer to poll on CQE
header in memory to determine if CQE is valid. Software needs
to make sure, that the reads of the CQE do not get re-ordered
so much that it ends up with an inconsistent view of the CQE.
To ensure that DMB barrier after read to first CQE cacheline
and before reading of the rest of the CQE is needed.
But having barrier for every CQE read will impact the performance,
instead use hardware CQ head and tail pointers to find the
valid number of CQEs.

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h
include/linux/soc/marvell/octeontx2/asm.h