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net/mlx5e: Use the aligned max TX MPWQE size
authorMaxim Mikityanskiy <maximmi@nvidia.com>
Tue, 27 Sep 2022 20:36:04 +0000 (13:36 -0700)
committerJakub Kicinski <kuba@kernel.org>
Thu, 29 Sep 2022 02:36:36 +0000 (19:36 -0700)
commit912e482e652b1e284e0e74b2bcaf174538255d8a
tree336e4f48312ccdffdccd0c1d97d94fcaaf620043tree | snapshot
parente4fd5799ae21ee09da2b7f38335fc1ccb3867842commit | diff
net/mlx5e: Use the aligned max TX MPWQE size

TX MPWQE size is limited to the cacheline-aligned maximum. Use the same
value for the stop room and the capability check.

Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/en/params.c diff | blob | history
drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h diff | blob | history
drivers/net/ethernet/mellanox/mlx5/core/en_main.c diff | blob | history
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