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(parent: aff200d) | patch
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
authorSwapnil Jakhade <sjakhade@cadence.com>
Fri, 28 Jan 2022 08:11:49 +0000 (13:41 +0530)
committerTom Rini <trini@konsulko.com>
Tue, 8 Feb 2022 16:00:04 +0000 (11:00 -0500)
commit8f9923c4cf0739863d753d2298fac44bac78407f
treebd865653bcf44e61975ebc2c2ee823ce0e500046tree | snapshot
parentaff200dc6c56bf52a4f7c9300281c44427c98c4ecommit | diff
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration

Add register sequences for PCIe + QSGMII PHY multilink configuration.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | history
"Das U-Boot" Source Tree.