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(parent: b10cfdf) | patch
drm/i915/pvc: Read correct RP_STATE_CAP register
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 5 May 2022 21:38:04 +0000 (14:38 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Tue, 10 May 2022 22:30:29 +0000 (15:30 -0700)
commit8c5e2b85c87eb26856be0f76a59108f7fb4f3286
treee0ab8d85dad6f0327c5567c0366b8f31bef5016ctree | snapshot
parentb10cfdfe9676874f73dff77c8aec7e7616f3f1aecommit | diff
drm/i915/pvc: Read correct RP_STATE_CAP register

The SoC registers, including RP_STATE_CAP, have moved to a new location
in GTTMMADR on Ponte Vecchio.  We need to update the register offset
accordingly.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-5-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_rps.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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