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Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Wed, 6 May 2020 14:47:31 +0000 (17:47 +0300)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 7 May 2020 06:44:40 +0000 (07:44 +0100)
commit88bdd61cd350c3861ec7045e216e408f5ae1c1ff
tree8c26324826f1e9eecb0f3cd6218e444a2f02da4etree | snapshot
parentf71da62357bd28f014d9a445179da24af8cfe5c7commit | diff
Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

This reverts commit 993cbdd5b2411f953bc4a831bbf01e22cfb75937.

L3 ro cache invalidation is part of the dword0 of pipe
control. Also it is not relevant to this gen.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506144734.29297-1-mika.kuoppala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_gpu_commands.h diff | blob | history
drivers/gpu/drm/i915/gt/intel_lrc.c diff | blob | history
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