]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Fix detection for a CMP-V PCH
authorImre Deak <imre.deak@intel.com>
Tue, 12 Nov 2019 10:46:08 +0000 (12:46 +0200)
committerImre Deak <imre.deak@intel.com>
Wed, 13 Nov 2019 12:03:15 +0000 (14:03 +0200)
commit8813b37a08fcd4bdeb44191e2bf66bef4734f6fb
tree7464f45806e2e46340f2de7aca491035d1be5160
parent961ce6aac92f6b13a51d28dc6f84322efdb4d044
drm/i915: Fix detection for a CMP-V PCH

According to internal documents I found for CMP PCHs the PCI ID 0xA3C1
belongs to a CMP-V chipset. Based on the same docs the programming of
the PCH is compatible with that of KBP. Fix up my previous wrong
assumption accordingly using the SPT programming which in turn is the
basis for KBP.

The original bug reporter verified that this is the correct PCH
identification (the only way we'll program valid DDC pin-pair values to
the GMBUS register) and the Windows team uses the same identification
(that is using the KBP programming model for this PCH).

I filed the necessary Bspec update requests (BSpec/33734).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112051
Fixes: dc377ca8fbc6 ("drm/i915: Add new CNL PCH ID seen on a CML platform")
Reported-and-tested-by: Cyrus <cyrus.lien@canonical.com>
Cc: Cyrus <cyrus.lien@canonical.com>
Cc: Timo Aaltonen <tjaalton@ubuntu.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191112104608.24587-1-imre.deak@intel.com
drivers/gpu/drm/i915/intel_pch.c
drivers/gpu/drm/i915/intel_pch.h