]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Tighten SAGV constraint for pre-tgl
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 5 Mar 2021 15:36:06 +0000 (17:36 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 12 Mar 2021 16:18:30 +0000 (18:18 +0200)
commit835508db9831c85e71f44e0b27c6197bcd639f3a
tree04289e9b085baca6c956b5e97b7b83076006643f
parent4a888e728c2775b356c4d5a1563fa72a88a66f1d
drm/i915: Tighten SAGV constraint for pre-tgl

Say we have two planes enabled with watermarks configured
as follows:
plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true
plane B: wm0=enabled/can_sagv=true,  wm1=disabled

This is possible since the latency we use to calculate
can_sagv may not be the same for both planes due to
skl_needs_memory_bw_wa().

In this case skl_crtc_can_enable_sagv() will see that
both planes have enabled at least one watermark level
with can_sagv==true, and thus proceeds to allow SAGV.
However, since plane B does not have wm1 enabled
plane A can't actually use it either. Thus we are
now running with SAGV enabled, but plane A can't
actually tolerate the extra latency it imposes.

To remedy this only allow SAGV on if the highest common
enabled watermark level for all active planes can tolerate
the extra SAGV latency.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210305153610.12177-3-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
drivers/gpu/drm/i915/intel_pm.c